Abstract
As was shown by P.C. Kanellakis and A.A. Shvartsman (1989), it is possible to combine efficiency and fault-tolerance in many PRAM algorithms in the presence of arbitrary dynamic fail-stop processor errors. Here we describe a technique for efficient and fault-tolerant simulation of arbitrary PRAM algorithms. Given a P-processor PRAM algorithm we simulate it efficiently and fault-tolerantly by a P'-processor CRCW PRAM algorithm, for P'≤P. The simulation is optimal for P'≤ P log2P.
Original language | English (US) |
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Pages (from-to) | 59-66 |
Number of pages | 8 |
Journal | Information Processing Letters |
Volume | 39 |
Issue number | 2 |
DOIs | |
State | Published - Jul 31 1991 |
Externally published | Yes |
Keywords
- Fault-tolerance
- PRAM
- efficiency
- parallel algorithms
ASJC Scopus subject areas
- Theoretical Computer Science
- Signal Processing
- Information Systems
- Computer Science Applications