TY - GEN
T1 - Assessing the Performance and Suitability of FPGAs as Hardware Accelerator for Software Programmers
AU - Mishra, Adarsh
AU - Ajith, K. J.
AU - Bhatt, Kislay
AU - Vaibhav, Kumar
AU - Duggal, Vibhuti
N1 - Publisher Copyright:
© 2022, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
PY - 2022
Y1 - 2022
N2 - Hardware accelerators have evolved into an important tool for meeting the ever-increasing performance demands of modern computation systems. In the modern high-performance computing domain, widely available hardware accelerators are PCIe-attached co-processors to which the host CPU can offload compute-intensive tasks. The goal of this paper is to determine whether FPGAs are a viable option as a hardware accelerator for software programmers, and if so, how their performance compares to existing processors/co-processors such as GPGPUs and CPUs in various types of HPC workloads. We can take advantage of recent advancements in high-level synthesis (HLS) tools, which enable simple programming and debugging for FPGAs. We chose OpenCL for programming because it supports a wide range of devices such as GPUs, FPGAs, DSPs, CPUs, and so on. We are using the Intel Devcloud setup for our experiments because it gives us access to modern Intel FPGAs, which can be used as hardware accelerators in conjunction with other resources such as GPGPUs and multicore processors.
AB - Hardware accelerators have evolved into an important tool for meeting the ever-increasing performance demands of modern computation systems. In the modern high-performance computing domain, widely available hardware accelerators are PCIe-attached co-processors to which the host CPU can offload compute-intensive tasks. The goal of this paper is to determine whether FPGAs are a viable option as a hardware accelerator for software programmers, and if so, how their performance compares to existing processors/co-processors such as GPGPUs and CPUs in various types of HPC workloads. We can take advantage of recent advancements in high-level synthesis (HLS) tools, which enable simple programming and debugging for FPGAs. We chose OpenCL for programming because it supports a wide range of devices such as GPUs, FPGAs, DSPs, CPUs, and so on. We are using the Intel Devcloud setup for our experiments because it gives us access to modern Intel FPGAs, which can be used as hardware accelerators in conjunction with other resources such as GPGPUs and multicore processors.
KW - FPGAs
KW - GPUs
KW - HPC
KW - Hardware abstraction
KW - Hardware acceleration
KW - OpenCL
KW - Re-configurability
UR - http://www.scopus.com/inward/record.url?scp=85136135425&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85136135425&partnerID=8YFLogxK
U2 - 10.1007/978-981-19-1018-0_44
DO - 10.1007/978-981-19-1018-0_44
M3 - Conference contribution
AN - SCOPUS:85136135425
SN - 9789811910173
T3 - Lecture Notes in Networks and Systems
SP - 511
EP - 520
BT - Advances in Distributed Computing and Machine Learning - Proceedings of ICADCML 2022
A2 - Rout, Rashmi Ranjan
A2 - Ghosh, Soumya Kanti
A2 - Jana, Prasanta K.
A2 - Tripathy, Asis Kumar
A2 - Sahoo, Jyoti Prakash
A2 - Li, Kuan-Ching
PB - Springer Science and Business Media Deutschland GmbH
T2 - 3rd International Conference on Advances in Distributed Computing and Machine Learning, ICADCML 2022
Y2 - 15 January 2022 through 16 January 2022
ER -