Cost-effective fpga implementation of parallel schmidt-samoa cryptosystem (SSC)

Schmidt-Samoa Cryptosystem (SSC) is a public key Cryptosystem. SSG is heavily based on modular arithmetic involving large prime number. In this paper, we consider a SSC that is used to secure the data over a communication system against vulnerabilities and attacks. We propose an efficient FPGA implementation of SSC cryptosystem that employs scalable arithmetic modules and effective number theory schemes in maximum parallelism exploitation. The provided simulation results show the advantage of using parallelization of system modules in optimizing the system performance of data security against attacks. On average, the encryption/decryption process of 128 − bit SSC registered a total delay of 125 ms approximately with maximum operational frequency of 40 MHz utilizing of 50% of the logic elements of Altera Cyclone IV FPGA EP4CGX22CF19C7 device and consuming 250 mW of thermal power. Consequently, the obtained results are attractive for FPGA designer of cryptographic algorithms with scalable design area, fast encryption/decryption processes and low power consumptions.