TY - JOUR
T1 - Oh-RAM! one and a half round atomic memory
AU - Hadjistasi, Theophanis
AU - Nicolaou, Nicolas
AU - Schwarzmann, Alexander A.
N1 - DBLP License: DBLP's bibliographic metadata records provided through http://dblp.org/ are distributed under a Creative Commons CC0 1.0 Universal Public Domain Dedication. Although the bibliographic metadata records are provided consistent with CC0 1.0 Dedication, the content described by the metadata records is not. Content may be subject to copyright, rights of privacy, rights of publicity and other restrictions.
PY - 2017
Y1 - 2017
N2 - Implementing atomic read/write shared objects in a message-passing system is an important problem in distributed computing. Considering that communication is the most expensive resource, efficiency of read and write operations is assessed primarily in terms of the needed communication and the associated latency. Attiya, Bar-Noy, and Dolev established that two communication round-trip phases involving in total four message exchanges are sufficient to implement atomic operations when a majority of processors are correct. Subsequently Dutta et al. showed that one round involving two communication exchanges is sufficient as long as the system adheres to certain constraints with respect to crashes on the number of readers and writers in the system. It was also observed that three exchanges are sufficient in some settings. This extended abstract presents work that explores algorithms where operations are able to complete in three message exchanges without imposing constraints on the number of participants, i.e., the aim is One and half Round Atomic Memory, hencethenameOh-RAM!Recently Hadjistasi et al. showed that three-exchange implementations are impossible in the MWMR (multi-writer/multi-reader) setting. This paper shows that this is achievable in the SWMR (single-writer/multi-reader) setting, and also achievable for read operations in the MWMR setting by “sacrificing” the performance of write operations. In particular, a SWMR implementation is presented, where reads complete in three and writes complete in two exchanges. Next, a MWMR implementation is given, where reads involve three and writes involve four exchanges. In light of the impossibility result these algorithms are optimal in terms of the number of communication exchanges. Both algorithms are then refined to allow some reads to complete in just two exchanges. These algorithms are evaluated and compared using the NS3 simulator with different topologies and operation loads.
AB - Implementing atomic read/write shared objects in a message-passing system is an important problem in distributed computing. Considering that communication is the most expensive resource, efficiency of read and write operations is assessed primarily in terms of the needed communication and the associated latency. Attiya, Bar-Noy, and Dolev established that two communication round-trip phases involving in total four message exchanges are sufficient to implement atomic operations when a majority of processors are correct. Subsequently Dutta et al. showed that one round involving two communication exchanges is sufficient as long as the system adheres to certain constraints with respect to crashes on the number of readers and writers in the system. It was also observed that three exchanges are sufficient in some settings. This extended abstract presents work that explores algorithms where operations are able to complete in three message exchanges without imposing constraints on the number of participants, i.e., the aim is One and half Round Atomic Memory, hencethenameOh-RAM!Recently Hadjistasi et al. showed that three-exchange implementations are impossible in the MWMR (multi-writer/multi-reader) setting. This paper shows that this is achievable in the SWMR (single-writer/multi-reader) setting, and also achievable for read operations in the MWMR setting by “sacrificing” the performance of write operations. In particular, a SWMR implementation is presented, where reads complete in three and writes complete in two exchanges. Next, a MWMR implementation is given, where reads involve three and writes involve four exchanges. In light of the impossibility result these algorithms are optimal in terms of the number of communication exchanges. Both algorithms are then refined to allow some reads to complete in just two exchanges. These algorithms are evaluated and compared using the NS3 simulator with different topologies and operation loads.
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U2 - 10.1007/978-3-319-59647-1_10
DO - 10.1007/978-3-319-59647-1_10
M3 - Article
AN - SCOPUS:85019771894
SN - 0302-9743
VL - abs/1610.08373
SP - 117
EP - 132
JO - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
JF - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
T2 - 5th International Conference on Networked Systems, NETYS 2017
Y2 - 17 May 2017 through 19 May 2017
ER -