Porting irregular reductions on heterogeneous CPU-GPU configurations

Xin Huo, Vignesh T. Ravi, Gagan Agrawal

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Scopus citations

Abstract

Heterogeneous architectures are playing a significant role in High Performance Computing (HPC) today, with the popularity of accelerators like the GPUs, and the new trend towards the integration of CPUs and GPUs. Developing applications that can effectively use these architectures is a major challenge. In this paper, we focus on one of the dwarfs in the Berkeley view on parallel computing, which are the irregular applications arising from unstructured grids. We consider the problem of executing these reductions on heterogeneous architectures comprising a multi-core CPU and a GPU. We have developed a Multi-level Partitioning Framework, which has the following features: 1) it supports GPU execution of irregular reductions even when the dataset size exceeds the size of the device memory, 2) it can enable pipelining of partitioning performed on the CPU, and the computations on the GPU, and 3) it supports dynamic distribution of work between the multi-core CPU and the GPU. Our extensive evaluation using two different irregular applications demonstrates the effectiveness of our approach.

Original languageEnglish (US)
Title of host publication18th International Conference on High Performance Computing, HiPC 2011
DOIs
StatePublished - 2011
Externally publishedYes
Event18th International Conference on High Performance Computing, HiPC 2011 - Bangalore, India
Duration: Dec 18 2011Dec 21 2011

Publication series

Name18th International Conference on High Performance Computing, HiPC 2011

Conference

Conference18th International Conference on High Performance Computing, HiPC 2011
CountryIndia
CityBangalore
Period12/18/1112/21/11

ASJC Scopus subject areas

  • Software

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