The impact of event processing flow on asynchronous server efficiency

Shungeng Zhang, Qingyang Wang, Yasuhiko Kanemasa, Huasong Shan, Liting Hu

Research output: Contribution to journalArticlepeer-review

Abstract

Asynchronous event-driven server architecture has been considered as a superior alternative to the thread-based counterpart due to reduced multithreading overhead. In this paper, we conduct empirical research on the efficiency of asynchronous Internet servers, showing that an asynchronous server may perform significantly worse than a thread-based one due to two design deficiencies. The first one is the widely adopted one-event-one-handler event processing model in current asynchronous Internet servers, which could generate frequent unnecessary context switches between event handlers, leading to significant CPU overhead of the server. The second one is a write-spin problem (i.e., repeatedly making unnecessary I/O system calls) in asynchronous servers due to some specific runtime workload and network conditions (e.g., large response size and non-trivial network latency). To address these two design deficiencies, we present a hybrid solution by exploiting the merits of different asynchronous architectures so that the server is able to adapt to dynamic runtime workload and network conditions in the cloud. Concretely, our hybrid solution applies a lightweight runtime request checking and seeks for the most efficient path to process each request from clients. Our results show that the hybrid solution can achieve from 10 to 90 percent higher throughput than all the other types of servers under the various realistic workload and network conditions in the cloud.

Original languageEnglish (US)
Article number8825817
Pages (from-to)565-579
Number of pages15
JournalIEEE Transactions on Parallel and Distributed Systems
Volume31
Issue number3
DOIs
StatePublished - Mar 1 2020
Externally publishedYes

Keywords

  • Asynchronous
  • efficiency
  • event-driven
  • internet servers
  • thread-based

ASJC Scopus subject areas

  • Signal Processing
  • Hardware and Architecture
  • Computational Theory and Mathematics

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