A method of deterministic simulation of fully operational parallel machines on the analogous machines prone to errors is developed. The simulation is presented for the exclusive-read exclusive-write (EREW) PRAM and the Optical Communication Parallel Computer (OCPC), but it applies to a large class of parallel computers. It is shown that simulations of operational multiprocessor machines on faulty ones can be performed with logarithmic slowdown in the worst case. More precisely, we prove that both a PRAM with a bounded fraction of faulty processors and memory cells and an OCPC with a bounded fraction of faulty processors can simulate deterministically their fault-free counterparts with O(logn) slowdown and preprocessing done in time O(log2 n). The fault model is as follows. The faults are deterministic (worst-case distribution) and static (do not change in the course of a computation). If a processor attempts to communicate with some other processor (in the case of an OCPC) or read a memory word (in the case of a PRAM) then it is immediately notified whether the operation was successful (fault-free addressee) or failed (faulty addressee). This is for the first time that a general fast deterministic simulation technique is designed for the EREW PRAM with the worst-case fault distribution. The simulation is designed in such a way that it relies only on a fraction of all the operational processors. During preprocessing, the active processors retrieve the original input provided to all processors before the simulation started. This is accomplished by adapting the information-dispersal method.