Parallel Algorithms with Processor Failures and Delays

Jonathan F. Buss, Paris C. Kanellakis, Prabhakar L. Ragde, Alex Allister Shvartsman

Research output: Contribution to journalArticlepeer-review

Abstract

We study efficient deterministic parallel algorithms on two models: restartable fail-stop CRCW PRAMs and asynchronous PRAMs. In the first model, synchronous processes are subject to arbitrary stop failures and restarts determined by an on-line adversary and involving loss of private but not shared memory; the complexity measures are completed work (where processors are charged for completed fixed-size update cycles) and overhead ratio (completed work amortized over necessary work and failures). In the second model, the result of the computation is a serialization of the actions of the processors determined by an on-line adversary; the complexity measure is total work (number of steps taken by all processors). Despite their differences, the two models share key algorithmic techniques. We present new algorithms for the Write-All problem (in which P processors write ones into an array of size N) for the two models. These algorithms can be used to implement a simulation strategy for any N processor PRAM on a restartable fail-stop P processor CRCW PRAM such that it guarantees a terminating execution of each simulated N processor step, with O(log2 N) overhead ratio, and O(min{N + P log2 N + M log N, N · P0.59}) (subquadratic) completed work (where M is the number of failures during this step's simulation). This strategy has a range of optimality. We also show that the Write-All requires N + Ω(P log P) completed/total work on these models for P ≤ N. & 1996 Academic Press, Inc.

Original languageEnglish (US)
Pages (from-to)45-86
Number of pages42
JournalJournal of Algorithms
Volume20
Issue number1
DOIs
StatePublished - Jan 1996
Externally publishedYes

ASJC Scopus subject areas

  • Control and Optimization
  • Computational Mathematics
  • Computational Theory and Mathematics

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